Practical aspects of high speed switched-capacitor decimation filter implementation

This publication has 10 references indexed in Scilit:

• Effects of coefficient inaccuracy in switched-capacitor transversal filters
  IEEE Transactions on Circuits and Systems, 1991
• A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
  IEEE Journal of Solid-State Circuits, 1990
• A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
• A switched-capacitor realization of multiple FIR filters on a single chip
  IEEE Journal of Solid-State Circuits, 1988
• Nonrecursive polyphase switched-capacitor decimators and interpolators
  IEEE Transactions on Circuits and Systems, 1985
• High-frequency CMOS continuous-time filters
  IEEE Journal of Solid-State Circuits, 1984
• Fully integrated active RC filters in MOS technology
  IEEE Journal of Solid-State Circuits, 1983
• Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology
  IEEE Transactions on Communications, 1982
• Switched-capacitor decimation and interpolation circuits
  IEEE Transactions on Circuits and Systems, 1980
• A sampled analog MOS LSI adaptive filter
  IEEE Journal of Solid-State Circuits, 1979