Power dissipation of VLSI array processing systems

This publication has 11 references indexed in Scilit:

• A model for estimating power dissipation in a class of DSP VLSI chips
  IEEE Transactions on Circuits and Systems, 1991
• Concurrent forms of signal processing algorithms
  IEEE Transactions on Circuits and Systems, 1989
• Power dissipation estimate by switch level simulation (CMOS circuits)
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
• Foreword (December 1986)
  IEEE Journal of Solid-State Circuits, 1986
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
  IEEE Transactions on Computers, 1986
• The Design of Optimal Systolic Arrays
  IEEE Transactions on Computers, 1985
• Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
  IEEE Journal of Solid-State Circuits, 1984
• New structure for an adaptive servomechanism controller
  IEE Proceedings D Control Theory and Applications, 1984
• Partitioned Matrix Algorithms for VLSI Arithmetic Systems
  IEEE Transactions on Computers, 1982
• Why systolic architectures?
  Computer, 1982