A study in the use of PLA-based macros
- 1 October 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (5) , 833-840
- https://doi.org/10.1109/jssc.1979.1051280
Abstract
Describes a study in which a PLA-based macro design of a small processor is carried out in the same technology as the original `random' logic design of the same processor. The objectives of the study were to determine gains or losses in `technology utilization' when a PLA-based approach is used to replace the more conventional `random' logic approach. The results in this case are a design of equal performance and density, with only one-third the power dissipation of the original design.Keywords
This publication has 5 references indexed in Scilit:
- High-Speed Dynamic Programmable Logic Array ChipIBM Journal of Research and Development, 1975
- An Introduction to Array LogicIBM Journal of Research and Development, 1975
- Hardware Implementation of a Small System in Programmable Logic ArraysIBM Journal of Research and Development, 1975
- MINI: A Heuristic Approach for Logic MinimizationIBM Journal of Research and Development, 1974
- Comparison of MOSFET logic circuitsIEEE Journal of Solid-State Circuits, 1973