An 8-Core 64-Thread 64b Power-Efficient SPARC SoC

1 February 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 108-590
https://doi.org/10.1109/isscc.2007.373611

Abstract

The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one times8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a die size of 342mm ² is implemented in a 11M 65nm triple-V_t CMOS process

Keywords

CLOCKS
ETHERNET NETWORKS
AGGREGATES
POWER SYSTEM RELIABILITY
PACKAGING
CRYPTOGRAPHY
PULSE GENERATION
DELAY
COUNTING CIRCUITS
MICROPROCESSORS

This publication has 1 reference indexed in Scilit:

Sparc T4: A Dynamically Threaded Server-on-a-Chip
IEEE Micro, 2012