The architectures and design of a 20-MHz real-time DSP chip set
- 1 April 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (2) , 338-348
- https://doi.org/10.1109/4.18594
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- A CMOS two-dimensional digital filter for TV picturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- VLSI Architecture for a one chip video median filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Generation of high speed CMOS multiplier-accumulatorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 20-ns CMOS micro DSP core for video-signal processingIEEE Journal of Solid-State Circuits, 1988
- Design of an image edge detection filter using the Sobel operatorIEEE Journal of Solid-State Circuits, 1988
- A Parallel Image Processor ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A micro-programmable realtime image processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A realtime image processing chip setPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Why systolic architectures?Computer, 1982
- A Separable Median Filter for Image Noise SmoothingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981