Chip level modeling and simulation

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Abstract
An approach to the modeling of LSI devices at the chip level is described. The complexity of these devices requires that higher level modeling techniques be developed. However, it is impor tant to preserve as much model accuracy as possible when developing high level models. In the approach described here, the chip level models are used to simulate not only device microoperations and internal memory, but also detailed inter face timing requirements. Modeling of such interface timing specifications as set up time, hold time, and minimum pulse width are possible. A modeling example is presented. Opera tion of the complete simulator is described. Two research ap plications of chip level modeling are discussed and an evalua tion of this approach to modeling and simulation is given.