CMOS circuit speed optimization based on switch level simulation

Publisher Website

6 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iscas.1988.15358

Abstract

No abstract available

Keywords

This publication has 4 references indexed in Scilit:

A true single-phase-clock dynamic CMOS circuit technique
IEEE Journal of Solid-State Circuits, 1987
Fully Dynamic Switch-Level Simulation of CMOS Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
FFT scaling in Domino CMOS gates
IEEE Journal of Solid-State Circuits, 1985
Optimization of device area and overall delay for CMOS VLSI designs
Proceedings of the IEEE, 1984