High performance clock distribution for CMOS ASICs

This publication has 5 references indexed in Scilit:

• Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI
  IEEE Journal of Solid-State Circuits, 1986
• Signal Delay in RC Tree Networks
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
• Aluminum Electromigration Under Pulsed D.C. Conditions
  8th Reliability Physics Symposium, 1983
• The largest minimal rectilinear steiner trees for a set ofn points enclosed in a rectangle with given perimeter
  Networks, 1979
• Electromigration Failure Under Pulse Test Conditions
  8th Reliability Physics Symposium, 1978