A 30ns 256K full CMOS SRAM

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 204-205
https://doi.org/10.1109/isscc.1986.1156880

Abstract

This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm × 13.2μ m.

Keywords

RANDOM ACCESS MEMORY
READ-WRITE MEMORY
POWER DISSIPATION
DRIVER CIRCUITS
ARTIFICIAL INTELLIGENCE
VERY LARGE SCALE INTEGRATION
CMOS TECHNOLOGY
ISOLATION TECHNOLOGY
PAPER TECHNOLOGY
MOSFETS

This publication has 3 references indexed in Scilit:

A 4.5ns 256K CMOS SRAM with tri-level word line
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
A 256K CMOS SRAM with variable-impedance loads
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
A 64Kb full CMOS RAM with divided word line structure
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983