Effective path selection for delay fault testing of sequential circuits

This publication has 17 references indexed in Scilit:

• AN ENHANCEMENT TO LSSD AND SOME APPLICATIONS OF LSSD IN RELIABILITY, AVAILABILITY, AND SERVICEABILIT
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Testable path delay fault cover for sequential circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Identifying redundant path delay faults in sequential circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Flags and algebra for sequential circuit VNR path delay fault test generation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests
  Journal of Electronic Testing, 1997
• Synthesis of delay-verifiable combinational circuits
  IEEE Transactions on Computers, 1995
• Exploiting multicycle false paths in the performance optimization of sequential logic circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
• Delay fault coverage and performance tradeoffs
  Published by Association for Computing Machinery (ACM) ,1993
• Timing verification using statically sensitizable paths
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• On Delay Fault Testing in Logic Circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987