Network Partitioning and Ordering for MOS VLSI Circuits

Abstract
This paper describes the algorithms used in a presimulation phase to partition an MOS digital network into various special subnetworks (or blocks) and to order these subnetworks for processing in a switch-level timing simulator such as MOSTIM [1]. A transistor-level SPICE2-type [3] description of the network is assumed to be provided. The key to the partitioning strategy is to divide the set of enhancement transistors into driver and pass transistors. The driver transistors are then grouped together in a de-connected sense to form multiple-input single-output combinatorial logic blocks, while the pass transistors are grouped together to form pass transistor blocks. A graph algorithm performs the partitioning step in computation time that is linear with the number of enhancement transistors. The partitioning step is an automatic process that is completely transparent to the user. The partitioned blocks are then ordered for simulation such that, whenever possible, a block is scheduled for processing only after all its input waveforms are known. A clear and precise notion of feedback among the various blocks in the partitioned network is introduced, and a distinction is made between feedback among different blocks and feedback internal to a block. It is shown that a good ordering for processing the blocks in a network is possible only in the absence of any form of feedback among the blocks. In case of a partitioned network with feedback, a linear time algorithm is presented that detects the strongly connected blocks, which are then flagged for simulation using special dynamic windowing techniques [4]. The strongly connected components are then topologically ordered for simulation.

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