Placement and Routing in 3D Integrated Circuits
Top Cited Papers
- 21 November 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 22 (6) , 520-531
- https://doi.org/10.1109/mdt.2005.150
Abstract
Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed under our 3D analysis and design optimization framework. These approaches address a dichotomy of design styles, both FPGA and ASIC. The factors that are important in each style are different, so that a one-size-fits-all approach is impractical, and therefore, we present separate approaches for 3D physical design for each of these technologies. Hence, our FPGA placement method uses a two-step optimization process that minimizes inter-tier vias first, followed by further optimization within and across tiers. In contrast, the ASIC flow uses cost function weighting to discourage, but not minimize, inter-tier crossings.Keywords
This publication has 11 references indexed in Scilit:
- Placement of thermal vias in 3-D ICs using various thermal objectivesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
- Multilevel Hypergraph Partitioning: Application In Vlsi DomainPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Three-dimensional place and route for FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabricationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fabrication technologies for three-dimensional integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fast timing-driven partitioning-based placement for island style FPGAsPublished by Association for Computing Machinery (ACM) ,2003
- An SOI-based three-dimensional integrated circuit technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A timing-constrained simultaneous global routing algorithmIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002
- Universal switch blocks for three-dimensional FPGA designPublished by Association for Computing Machinery (ACM) ,1999
- VPR: a new packing, placement and routing tool for FPGA researchPublished by Springer Nature ,1997