Design and programming of a flexible, cost-effective systolic array cell for digital signal processing
- 1 July 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Acoustics, Speech, and Signal Processing
- Vol. 38 (7) , 1198-1210
- https://doi.org/10.1109/29.57547
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- SAC: a systolic array controller chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Complexity of Matrix Product on a Class of Orthogonally Connected Systolic ArraysIEEE Transactions on Computers, 1987
- Array architectures for iterative algorithmsProceedings of the IEEE, 1987
- Programming Environments for Systolic ArraysPublished by SPIE-Intl Soc Optical Eng ,1986
- A One-Third Gigaflop Systolic Linear Algebra ProcessorPublished by SPIE-Intl Soc Optical Eng ,1984
- An interactive system for VLSI chip physical designIBM Journal of Research and Development, 1984
- Wafer-scale integration and two-level pipelined implementations of systolic arraysJournal of Parallel and Distributed Computing, 1984
- Concurrent Systems for Image AnalysisPublished by Springer Nature ,1984
- Design of the PSC: A Programmable Systolic ChipPublished by Springer Nature ,1983