A Digital Quarter Square Multiplier
- 1 March 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-29 (3) , 258-261
- https://doi.org/10.1109/tc.1980.1675558
Abstract
An application of the quarter square multiplication technique used in analog computing is proposed for digital multiplication. Significant savings in storage requirements for ROM- implemented product tables are demonstrated. A two's complement multiplication circuit utilizing the digital quarter square technique is presented.Keywords
This publication has 3 references indexed in Scilit:
- High-Speed Monolithic Multipliers for Real-Time Digital Signal ProcessingComputer, 1978
- A Compact High-Speed Parallel Multiplication SchemeIEEE Transactions on Computers, 1977
- Fast MultipliersIEEE Transactions on Computers, 1970