A Compact High-Speed Parallel Multiplication Scheme
- 1 October 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-26 (10) , 948-957
- https://doi.org/10.1109/tc.1977.1674730
Abstract
This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.Keywords
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