Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
- 1 March 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (3) , 258-280
- https://doi.org/10.1109/t-c.1975.224207
Abstract
A family of switching networks, called "arithmetic networks," is investigated. The elementary units of these networks are generalizations of full adders that can process input signals of different weights.Keywords
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