Dynamic leakage cut-off scheme for low-voltage SRAM's
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic loadPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low-power CMOS design through VTH control and low-swing circuitsPublished by Association for Computing Machinery (ACM) ,1997