Hardware-efficient fair queueing architectures for high-speed networks
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2 (0743166X) , 638-646
- https://doi.org/10.1109/infcom.1996.493359
Abstract
In emerging communication networks (B-ISDN based on asynchronous transfer mode (ATM) technology), a single link may carry traffic for thousands of connections with different traffic parameters and quality-of-service requirements. High-speed links, coupled with small packet/cell sizes, require efficient switch architectures that can handle cell arrivals and departures every few microseconds, or faster. This paper presents a collection of self-clocked fair queueing (SCFQ) architectures amenable to efficient hardware implementation in network switches. Exact and approximate implementations of SCFQ efficiently handle a moderate range of connection bandwidth parameters, while hierarchical arbitration schemes scale to a large range of throughput requirements. Simulation experiments demonstrate that these architectures divide link bandwidth fairly on a small time scale, preserving connection bandwidth and burstiness properties.Keywords
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