A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache
- 1 January 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 315-324
- https://doi.org/10.1109/isscc.2006.1696062
Abstract
A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm 2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modesKeywords
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