Fully depleted dual-gated thin-film SOI p-MOSFET with an isolated buried polysilicon backgate
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 135-136
- https://doi.org/10.1109/soi.1995.526497
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Interface characterization of fully depleted SOI MOSFETs by a threshold-voltage methodSolid-State Electronics, 1993
- Fully planar method for creating adjacent ‘‘self-isolating’’ silicon-on-insulator and epitaxial layers by epitaxial lateral overgrowthApplied Physics Letters, 1992