Single event upset test structures for digital CMOS application specific integrated circuits

1 December 1993

journal article
research article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 40 (6) , 1703-1708
https://doi.org/10.1109/23.273490

Abstract

An approach has been developed for the design and utilization of SEU test Structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips

This publication has 10 references indexed in Scilit:

On the suitability of non-hardened high density SRAMs for space applications
IEEE Transactions on Nuclear Science, 1991
Simulation of SEU transients in CMOS ICs
IEEE Transactions on Nuclear Science, 1991
Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs
IEEE Transactions on Nuclear Science, 1990
Response of a DRAM to single-ion tracks of different heavy-ion species and stopping powers
IEEE Transactions on Nuclear Science, 1990
SEU characterization of a hardened CMOS 64K and 256K SRAM
IEEE Transactions on Nuclear Science, 1989
SEU characterization of hardened CMOS SRAMs using statistical analysis of feedback delay in memory cells
IEEE Transactions on Nuclear Science, 1989
SEU test techniques for 256 K static RAMs and comparisons of upsets by heavy ions and protons
IEEE Transactions on Nuclear Science, 1988
Techniques of Microprocessor Testing and SEU-Rate Prediction
IEEE Transactions on Nuclear Science, 1985
Simulation Approach for Modeling Single Event Upsets on Advanced CMOS SRAMS
IEEE Transactions on Nuclear Science, 1985
Single Event Upset Rate Predictions for Complex Logic Systems
IEEE Transactions on Nuclear Science, 1984