A 33-ns 64-Mb DRAM with Master-Wordline Architecture

1 September 1992

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 131-134
https://doi.org/10.1109/esscirc.1992.5468392

Abstract

A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.

Keywords

RANDOM ACCESS MEMORY
RESERVOIRS
DRIVER CIRCUITS
THRESHOLD VOLTAGE
VOLTAGE CONTROL
CAPACITANCE
CMOS TECHNOLOGY
BOOSTING
DECODING
SURFACE RESISTANCE

This publication has 1 reference indexed in Scilit:

A 4Mb DRAM with double-buffer static-column architecture
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005