Simulation of transients in VLSI packaging interconnections

Abstract

An approach to electrical analysis of VLSI packaging interconnections using computer simulation is discussed. Corresponding simulation software developed during the course of research on VLSI interconnections is described. Examples of application to prototypical interconnections (two-transmission-line systems joined by a lumped-parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. Simulation results for the above examples are presented and analyzed. The current status of work is discussed, and directions of future research are delineated.

Keywords

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