Numerical and experimental investigations of large IC flip chip attach
- 1 January 2000
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1338-1346
- https://doi.org/10.1109/ectc.2000.853353
Abstract
Because flip chips can achieve high electrical interconnect speed, high density, and low profiles, a team from the Fraunhofer Institute for Reliability and Microintegration in Berlin and from Georgia Tech undertake a study examining the extreme limits of flip chip input/output (I/O) capabilities and physical dimensions. Their starting point is a SIA estimate of memory requirements, based on Moore's Law, for the year 2012. In order to study the limitations of flip chip technology the groups are working on both, advanced thermomechanical simulation and hands-on interconnection technology resulting in the design of four flip chips. They have the dimensions of 10/spl times/10 mm/sup 2/, 20/spl times/20 mm/sup 2/, 30/spl times/30 mm/sup 2/, and 40/spl times/40 mm/sup 2/. With these designs both, the simulation and the interconnection technology departments of Fraunhofer IZM start to evaluate the feasibility of flip chips beyond 20/spl times/20 mm/sup 2/.Keywords
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