Do chip size limits exist for DCA?

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Abstract
Solder joints, the most widely used flip chip on board (FCOB) interconnects, have relatively low structural compliance due to the large thermal expansion mismatch between Si die and organic substrate. The PWB CTE is almost an order of magnitude greater than that of the IC. Under operating and testing conditions, this mismatch subjects solder joints to large creep strains and leads to early solder joint failure. FCOB structure reliability can be enhanced by applying an epoxy-based underfill between chip and substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate to constrain the CTE mismatch locally. However, CTE mismatch effects are assumed to become more severe with increasing chip size. Even with the use of underfill, it is supposed that there are limits on chip size in flip chip applications. Fraunhofer Institute IZM/Technical University are collaborating with Georgia Tech to study fundamental limits of direct chip attach. The objectives are: to understand material and mechanical issues related to thermo-mechanical reliability of direct chip attach; to determine fundamental chip size limits by taking process conditions, process-induced defects, underfill material property requirements, geometry limitations and service environment into consideration; to investigate the impact of geometrical, material and operating parameters on FCOB assembly thermomechanical reliability and to determine an optimum combination of parameters to minimize delamination, solder joint fatigue, chip cracking and/or excessive warpage; to validate FEA simulations experimentally.

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