A state space decomposition algorithm for approximate FSM traversal
- 1 January 1994
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- ATPG aspects of FSM verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient implementation of a BDD packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Implicit state enumeration of finite state machines using BDD'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential circuit verification using symbolic model checkingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Redundancy identification/removal and test generation for sequential circuits using implicit state enumerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Algorithms for approximate FSM traversalPublished by Association for Computing Machinery (ACM) ,1993
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970