Recent developments in parallel processing
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15206149,p. 2461-2467
- https://doi.org/10.1109/icassp.1989.266966
Abstract
The author advocates a concentration on two main classes of highly parallel architecture rather than a proliferation, which confuses the direction of software engineering developments. He discusses the two classes. DAP and supernode transputer arrays, and compares their performance. He concludes that the idea of welding together the SIMD and MIMD architectures to provide a very general capability machine should be discouraged. Instead, their individual versatility suggests that either could be used in many roles, and the complications of data interfacing and dual standards of programming data interfacing are unnecessary.Keywords
This publication has 9 references indexed in Scilit:
- Stereo matching of satellite images with transputersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A VLSI chip set for a massively parallel architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Virtual timeACM Transactions on Programming Languages and Systems, 1985
- Control Ordered Sonar Hardware (COSH)—a hardware based signal processing graph implementationIEE Proceedings F Communications, Radar and Signal Processing, 1984
- Speech recognition on a distributed array processorElectronics Letters, 1983
- A shared resource algorithm for distributed simulationACM SIGARCH Computer Architecture News, 1982
- Asynchronous distributed simulation via a sequence of parallel computationsCommunications of the ACM, 1981
- Time, clocks, and the ordering of events in a distributed systemCommunications of the ACM, 1978
- Some Computer Organizations and Their EffectivenessIEEE Transactions on Computers, 1972