Sub-30-nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process
- 9 July 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 29 (7) , 765-767
- https://doi.org/10.1109/led.2008.2000915
Abstract
We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents of 25-nm D-FUSI CMOS transistors increased by 15% more than those of the control.Keywords
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