Complexity-effective superscalar processors
- 1 May 1997
- proceedings article
- Published by Association for Computing Machinery (ACM)
- Vol. 25 (2) , 206-218
- https://doi.org/10.1145/264107.264201
Abstract
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is de-fined. Then the specific areas of register renaming, instruction win-dow wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated for feature sizes of, , andKeywords
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