Retiming of circuits with single phase transparent latches

10 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 86-89
https://doi.org/10.1109/iccd.1991.139850

Abstract

An algorithm is developed for the retiming of single phase sequential circuits with level sensitive (transparent) latches. A set of constraints that permit retiming and optimal clock cycle computation are also developed. It is shown that a design with edge-triggered latches may be tested for speed-up using transparent latches.

Keywords

This publication has 4 references indexed in Scilit:

Retiming of circuits with single phase transparent latches
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Retiming and resynthesis: optimizing sequential networks with combinational techniques
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Optimizing synchronous systems
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981