CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- ATV: an abstract timing verifierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pearl: a CMOS timing analyzerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Analysis and design of latch-controlled synchronous digital circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latchesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989