Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 46 (11) , 2195-2200
- https://doi.org/10.1109/16.796296
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Simulation-based assessment of 50 nm double-gate SOI CMOS performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 0.10 μm gate length CMOS technology with 30 Å gate dielectric for 1.0 V-1.5 V applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Electron and hole quantization and their impact on deep submicron silicon p- and n-MOSFET characteristicsIEEE Transactions on Electron Devices, 1997
- Compact non-local modeling of impact ionization in SOI MOSFETs for optimal CMOS device/circuit designSolid-State Electronics, 1996
- Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET'sIEEE Transactions on Electron Devices, 1995
- The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain betaIEEE Electron Device Letters, 1992
- Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?Published by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Subbreakdown drain leakage current in MOSFETIEEE Electron Device Letters, 1987