Parallel model evaluation for circuit simulation on the PACE multiprocessor
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
- A new O(n log n) scheduling heuristic for parallel decomposition of sparse matricesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A multiprocessor architecture for circuit simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Direct circuit simulation algorithms for parallel processing (VLSI)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Circuit simulation on shared-memory multiprocessorsIEEE Transactions on Computers, 1988
- Small-signal MOSFET models for analog circuit designIEEE Journal of Solid-State Circuits, 1982