A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)
- 28 September 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 142-517
- https://doi.org/10.1109/isscc.2004.1332634
Abstract
A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.Keywords
This publication has 2 references indexed in Scilit:
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- 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003