Layout compaction with attractive and repulsive constraints

Publisher Website

4 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/dac.1990.114885

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
Improved Compaction by Minimized Length of Wires
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983