Arrangement of latches in scan-path design to improve delay fault coverage
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 387-393
- https://doi.org/10.1109/test.1990.114046
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A method of delay fault test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Transition Fault SimulationIEEE Design & Test of Computers, 1987
- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984