A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 951-961
- https://doi.org/10.1109/4.34077
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- Perspective on BiCMOS VLSIsIEEE Journal of Solid-State Circuits, 1988
- Design considerations for a high-performance 3-μm CMOS analog standard-cell libraryIEEE Journal of Solid-State Circuits, 1987
- CMOS voltage references using lateral bipolar transistorsIEEE Journal of Solid-State Circuits, 1985
- A 20-V four-quadrant CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1985
- MOS transistors operated in the lateral bipolar mode and their application in CMOS technologyIEEE Journal of Solid-State Circuits, 1983
- A four-quadrant analog divider multiplier with 0.01% distortionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982
- A high-speed low-power Hi-CMOS 4K static RAMIEEE Transactions on Electron Devices, 1979
- A CMOS voltage referenceIEEE Journal of Solid-State Circuits, 1978
- A precise four-quadrant multiplier with subnanosecond responseIEEE Journal of Solid-State Circuits, 1968