High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz
- 25 July 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (8) , 1658-1661
- https://doi.org/10.1109/JSSC.2005.852420
Abstract
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-/spl mu/m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.Keywords
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