Optimizing and Controlling the Radiation Hardness of a Si-Gate CMOS Process

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Abstract
A quick-turnaround technique is presented for optimizing the radiation hardness of parts produced by a Si-gate CMOS process. The technique involves (1) fabricating MOS capacitors on control wafers that can be "pulled" at different stages during the fabrication process, and (2) defining "hardness" in terms of the amount of radiation-induced charge. We demonstrate the use of this technique in monitoring radiation hardness before and after key process steps, as well as in determining the cumulative effects of many process steps on hardness. It is shown that the optimum temperature for gate oxidation in dry O2 is 1000°C for both Al- and Si-gate technologies. In addition, In-Source evaporated Al is a preferred process step over sputtered Al deposition for an Al-gate technology. By choosing process steps that optimize hardness, the hardness of parts fabricated using a Si-gate CMOS process can be increased by over an order of magnitude. Finally, we report a different electric field dependence for the buildup of interface states in Alversus Si-gate technologies.

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