Pipeline interleaved programmable DSP's: Architecture
- 1 September 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Acoustics, Speech, and Signal Processing
- Vol. 35 (9) , 1320-1333
- https://doi.org/10.1109/tassp.1987.1165274
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Architecture of a digital signal processorIBM Journal of Research and Development, 1985
- An NMOS digital signal processor with multiprocessing capabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Optimal choice of intermediate latching to maximize throughput in VLSI circuitsIEEE Transactions on Acoustics, Speech, and Signal Processing, 1984
- Experience with pipelined multiple instruction streamsProceedings of the IEEE, 1984
- The real-time signal processorIEEE Transactions on Acoustics, Speech, and Signal Processing, 1983
- Data Flow LanguagesComputer, 1982
- A microcomputer with digital signal processing capabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Architecture of a Programmable Digital Signal ProcessorIEEE Transactions on Computers, 1982
- Computer architecture for signal processingProceedings of the IEEE, 1975
- Some Computer Organizations and Their EffectivenessIEEE Transactions on Computers, 1972