Rounding algorithms for IEEE multipliers
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 176-183
- https://doi.org/10.1109/arith.1989.72824
Abstract
Several technology independent rounding algorithms for multiplying normalized numbers are presented. The first is a simple rounding algorithm suitable for software simulation or moderate performance hardware multipliers. The next two algorithms are parallel addition schemes suitable for high-performance VLSI multipliers. One of them eliminates the carry produced by the lower-order bits from the critical path. Several methods for computing the sticky bit are also presented. Included is a new fast and efficient technique for computing the sticky bit directly from the carry-save form without undergoing the expense of a carry-propagate addition.Keywords
This publication has 6 references indexed in Scilit:
- A 1,000,000 transistor microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A Pipelined 64x64b Iterative Array MultiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Roundings in Floating-Point ArithmeticIEEE Transactions on Computers, 1973
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951