A Suggestion for a High-Speed Parallel Binary Divider
- 1 January 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-21 (1) , 42-55
- https://doi.org/10.1109/t-c.1972.223430
Abstract
A family of four procedures to compute the inverse 1/X of a given binary number X normalized between 0.5 and 1 is described. The quotient is obtained in redundant binary form, i.e., in a base 2 code in which digits can assume any positive or negative integer value. All methods here described can be implemented by combinatorial networks; the dividers realized in this way are very fast because all carry propagations take place at the same time.Keywords
This publication has 8 references indexed in Scilit:
- A simple technique for digital divisionCommunications of the ACM, 1967
- A Division Method Using a Parallel MultiplierIEEE Transactions on Electronic Computers, 1967
- Divide-and-correct methods for multiple precision divisionCommunications of the ACM, 1964
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- A Class of Binary Divisions Yielding Minimally Represented QuotientsIRE Transactions on Electronic Computers, 1962
- Computer Multiplication and Division Using Binary LogarithmsIEEE Transactions on Electronic Computers, 1962
- An Algorithm for Rapid Binary DivisionIEEE Transactions on Electronic Computers, 1961
- A mathematical procedure for machine divisionCommunications of the ACM, 1959