5-Gbit/s Si integrated regenerative demultiplexer and decision circuit
- 1 June 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (3) , 385-389
- https://doi.org/10.1109/JSSC.1987.1052736
Abstract
A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.Keywords
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