A 150 MHz 8-banks 256 Mb synchronous DRAM with wave pipelining methods
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- A 200mhz 16mbit Synchronous Dram With Block Access ModePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequencyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Wave-pipelining: is it practical?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993