A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology
- 1 October 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (5) , 319-323
- https://doi.org/10.1109/jssc.1973.1050410
Abstract
For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured.Keywords
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