Adding a vector unit to a superscalar processor
- 1 May 1999
- proceedings article
- Published by Association for Computing Machinery (ACM)
Abstract
The focus of this paper is on adding a vector unit to a superscalarcore, as a way to scale current state of the art superscalarprocessors. The proposed architecture has a vectorregister file that shares functional units both with the integerdatapath and with the floating point datapath. A key point inour proposal is the design of a high performance cache interfacethat delivers high bandwidth to the vector unit at a lowcost and low latency. We propose a double-banked cache withalignment...Keywords
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