A 32 K ASIC synchronous RAM using a two-transistor basic cell
- 1 February 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (1) , 57-61
- https://doi.org/10.1109/4.16302
Abstract
A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K*32, 2 K*16, 4 K*8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW.Keywords
This publication has 2 references indexed in Scilit:
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- A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architectureIEEE Journal of Solid-State Circuits, 1985