Transparent-refresh DRAM (TReD) using dual-port DRAM cell
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed from a cumbersome refresh control without access-time degradation. The TReD cell size is about 1/2.5 of a 4-transistor SRAM (static RAM) cell, so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM cell, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments.Keywords
This publication has 7 references indexed in Scilit:
- Circuit technologies for 16Mb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 256K CMOS SRAM with internal refreshPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- 4Mb pseudo/virtually SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A 32b microprocessor with on-chip 2Kbyte instruction cachePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- 1-Mbit virtually static RAMIEEE Journal of Solid-State Circuits, 1986
- A 1Mb CMOS DRAM with fast page and static column modesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A low power 46 ns 256 kbit CMOS static RAM with dynamic double word lineIEEE Journal of Solid-State Circuits, 1984