High-level synthesis from VHDL with exact timing constraints

This publication has 13 references indexed in Scilit:

• Percolation based synthesis
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• ASIC design using the high-level synthesis system CALLAS: a case study
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• SALSA: a new approach to scheduling with timing constraints
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• High-Level VLSI Synthesis
  Published by Springer Nature ,1991
• Path-based scheduling for synthesis
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
• The high-level synthesis of digital systems
  Proceedings of the IEEE, 1990
• Relative scheduling under timing constraints
  Published by Association for Computing Machinery (ACM) ,1990
• Three competing design methodologies for ASIC's: architectual synthesis, logic synthesis, logic synthesis and module generation
  Published by Association for Computing Machinery (ACM) ,1989
• Synthesizing circuits from behavioural descriptions
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
• Automatic production of controller specifications from control and timing behavioral descriptions
  Published by Association for Computing Machinery (ACM) ,1989