When are transmission-line effects important for on-chip interconnections

22 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 704-712
https://doi.org/10.1109/ectc.1997.606248

Abstract

Short, medium and long on-chip interconnections having line widths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Keywords

This publication has 4 references indexed in Scilit:

Calculation of multi-port parameters of electronic packages using a general purpose electromagnetics code
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development, 1995
Performance trends in high-end processors
Proceedings of the IEEE, 1995
High-speed signal propagation on lossy transmission lines
IBM Journal of Research and Development, 1990